1. Field of the Disclosure
The present disclosure generally relates to transmitter interconnect interfaces and, more particularly, to clock mismatch compensation between a transmitter interconnect interface and a receiver interconnect interface.
2. Description of the Related Art
In many systems, the transmit side and receive side of an interconnect may operate using independent clock sources, which can introduce a frequency mismatch. To compound this problem, certain serial interconnect specifications, such as the Peripheral Component Interconnect Express (PCIe) specification, permit the use of spread spectrum clocking, and may permit multiple spread spectrum clock domains to be used in a system, which can result in an even greater clock mismatch in the event that one side is using spread spectrum clocking (SSC) and the other is not, or in the event that one side is in one spread spectrum clock domain and the other side is in a different spread spectrum clock domain. Many interconnect specifications attempt to address the potential for clock frequency mismatch by specifying the insertion of skip ordered sets into a transmitted datastream, such that the skip ordered sets can be dropped from the data stream or stored in an elastic buffer at the receive side so as to prevent buffer overflow/underflow. However, these specifications call for a fixed rate of insertion of skip ordered sets that reflects a worst-case frequency mismatch scenario, and thus waste interconnect bandwidth.